1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
2. Description of the Related Art
In semiconductor devices such as a memory, an increase in capacity and a shrinking in size are desired. Particularly in a memory cell array shrinking of the width of the interconnections, and narrowing of the pitch between adjacent ones of the interconnections have been in progress along with shrinking of the interconnections. When the pitch of the interconnections is narrowed, the capacitances between the interconnections become conspicuous. To reduce the capacitances, mutually facing areas of adjacent ones of the lines are reduced by thinning the thickness of an interconnection. On the other hand, in a control circuit (peripheral circuit portion) or the like, it is required that a power supply is reduced and the interconnections have low resistances. For this reason, it is necessary that interconnection lines having relatively wide widths should be arranged in the same interconnection layer where the miniaturized interconnections having a narrower pitch are disposed.
In semiconductor devices of recent years, damascene interconnections using copper (Cu) having a relatively low specific resistance have been utilized. A case is considered in which, while Cu interconnections in a memory cell portion are made as thin as possible, Cu interconnections in a peripheral circuit portion are made relatively thick. For example, in a case in which Cu interconnections are formed by use of an embedding method, the Cu interconnections are formed to have upper faces in a single plane, but to have lower faces at different levels. The thicknesses of the interconnection layers are appropriately adjusted as a result.
For example, there is disclosed a method of forming interconnections in a semiconductor device (refer to, for example, Japanese Patent Application Publication No. 2000-114259). In the method, a groove interconnection forming work (opening) is performed by etching an interlayer film that is laminated on tungsten (W) plugs formed in contact holes; thereafter, an interconnection metal made of aluminum (Al) or Cu is embedded in interconnection grooves formed through this groove interconnection forming work. The depths of the different interconnection grooves are varied due to a micro-loading effect during the groove interconnection forming work. The material of the plugs and the embedded material are not limited to W and Cu, respectively, but are different from each other in many cases.
According to the disclosed forming method, an insulating film having a wider opening width is etched more deeply than an insulating film having a narrower opening width, and thus an interconnection having a smaller cross-sectional area and an interconnection having a larger cross-sectional area can be formed. However, since the W plug remains scarcely etched, the interconnection having a larger cross-sectional area comes to have a shape in which the W plug intrudes deeply into the interconnection metal. If a W plug intrudes deeply into an interconnection metal, an embedding defect occurs in which a void and the like are formed in the interconnection metal on a side face of the W plug or in the vicinity of the side face. Additionally, there arises a problem that, because the interconnection metal on the upper face of the W plug is formed relatively thinly, and a part where a current density is high is generated as a result, the chance of occurrence of electromigration increases. When at least any one of the above-mentioned embedding defect and electromigration occurs, the interconnection resistance increases, and the performance of the semiconductor device is impeded.